Gate-All-Around: The Next Era of Transistors

The transistor, a marvel born from the crucible of post-war innovation in 1947, stands as a testament to humanity’s relentless pursuit of progress.

Its invention, lauded with a Nobel Prize for Walter Brattain, John Bardeen, and William Shockley, didn’t just create a new electronic component; it ignited an unseen revolution, fundamentally reshaping every facet of modern life.

From the sprawling data centers powering artificial intelligence to the miniature devices nestled in our pockets, transistors are the silent workhorses, amplifying and switching electronic signals with astonishing precision.

The sustained demand, evidenced by a near doubling of power transistor sales from $10 billion to $18.6 billion between 2008 and 2019, underscores their irreplaceable role and the perpetual quest for ever-greater efficiency and capability.

For decades, silicon reigned supreme as the bedrock of transistor technology.

Yet, as the digital age hurtles forward, demanding ever-smaller, more powerful, and less power-hungry chips, the physical limits of silicon scaling have become a pressing concern.

This challenge has pushed researchers to explore new materials and radical architectural designs.

Enter a groundbreaking development from the Institute of Industrial Science at the University of Tokyo, poised to redefine the very essence of transistor fabrication.

A team, led by Alan Chen and Masaharu Kobayashi, has unveiled a significant leap forward, moving beyond traditional silicon to craft a transistor from gallium-doped indium oxide (InGaOx).

This crystalline oxide material boasts an orderly lattice, perfectly suited for superior electron mobility, a critical factor in chip performance.

The ingenuity doesn’t stop at the material.

The Tokyo team’s breakthrough integrates InGaOx into a “gate-all-around” (GAA) structure.

Imagine the gate, which dictates whether current flows or not, not just sitting atop the channel but entirely enveloping it.

This complete encirclement significantly enhances control, boosts efficiency, and improves scalability compared to older, planar gate designs.

A key hurdle with indium oxide, as explained by Kobayashi, lies in its oxygen-vacancy defects, which can compromise device stability.

By strategically doping it with gallium, the researchers effectively suppressed these vacancies, fortifying the transistor’s reliability.

The meticulous process involved atomic-layer deposition, building the InGaOx film one atomic layer at a time, followed by heating to crystallize the structure, optimizing it for electron flow.

This meticulous engineering has yielded a metal oxide-based field-effect transistor (MOSFET) with an impressive mobility of 44.5 cm²/Vs, demonstrating stable operation for nearly three hours under stress – a promising indicator for real-world applications.

The gate-all-around architecture itself is the cornerstone of this next generation of semiconductor technology.

Unlike its predecessor, the FinFET, where the gate contacted the channel on three sides, GAA transistors achieve continuous scaling by surrounding the channel on all four sides.

This superior gate control dramatically reduces leakage current, a persistent bane of miniaturization, and simultaneously increases the drive current, leading to enhanced chip performance.

The secret lies in the use of vertically stacked nanosheets, allowing chipmakers unprecedented flexibility.

Wider nanosheets can be employed for applications demanding higher drive current, while narrower ones optimize power consumption, offering a tailored approach for diverse chip designs.

This versatility, combined with the potential for cost-effective manufacturing, positions GAA transistors to become the dominant paradigm in advanced chip production, underpinning everything from 5G connectivity and immersive gaming to cutting-edge AI solutions, medical technology, and automotive systems.

While the first GAA technology was demonstrated as early as 1986, it was only in 2022 that Samsung made history by manufacturing the first GAA-enabled chip at a 3-nanometer processor node with its Multi-Bridge-Channel FET (MBCFET).

But the race for dominance in this critical arena is heating up, and Intel (INTC) is emerging as a formidable contender, actively bringing GAA transistor technology into mass production.

Their 18A process, featuring Intel’s proprietary RibbonFET (a GAA transistor offering up to 15% better performance per watt than FinFET) and the innovative PowerVia backside power delivery technology, is a strategic move to reassert their leadership.

PowerVia, by relocating power rails to the backside of the chip, frees up critical front-side space for routing, improving density and reducing power delivery droop.

This holistic approach, backed by a robust ecosystem of over 35 industry partners, underscores Intel’s commitment to delivering high-performance, energy-efficient solutions for the data-intensive workloads of today and tomorrow, particularly in the burgeoning fields of generative AI and high-performance computing.

Intel’s continued evolution with variants like 18A-P and 18A-PT further solidifies its roadmap for advanced 3DIC designs, crucial for pushing the boundaries of integration and scalability.

Yet, the path forward is not without its formidable challenges.

The relentless pursuit of miniaturization introduces complex engineering hurdles.

Researchers acknowledge issues like self-heating, which can degrade performance, and mechanical stability during fabrication, where the delicate nanosheet structures must maintain their integrity.

Device variability, stemming from microscopic imperfections like line-edge roughness or non-uniform material deposition, remains a constant battle.

Furthermore, the thermal intermixing of silicon-germanium (SiGe) stacks during manufacturing poses a risk to channel integrity.

While novel solutions like diamond-on-silicon substrates are being explored for self-heating, their viability for high-volume manufacturing remains uncertain.

Beyond the transistor itself, the scientific community is increasingly emphasizing the importance of innovating in interconnects and power delivery.

Concepts like the buried power rail (BPR), which aims to move power rails below the transistors, promise further area savings but introduce complex backside patterning and alignment challenges.

Despite these complexities, the consensus is clear: GAA is a major milestone in silicon lithography, poised to take the baton from FinFETs and propel the semiconductor industry to new heights of scaling.

The superior gate control and improved short-channel effect (SCE) suppression offered by GAA FETs position them as the definitive choice for 3-nanometer technology nodes and beyond.

However, the delicate balance between performance gains and power consumption, particularly with advancements like negative capacitance GAA FETs, will continue to be a focal point of research.

The journey of the transistor, from a curious laboratory invention to the invisible force driving our digital world, is a continuous saga of innovation.

For now, GAA transistors are not just showing promising results; they are leading the charge into a future where computing power knows fewer bounds, enabling the next wave of transformative technologies.