TSMC Unveils Revolutionary Chip Packaging Technology to Meet Rising AI Demands

The world of semiconductors is on the cusp of a groundbreaking evolution as Taiwan Semiconductor Manufacturing Company (TSMC) unveils its ambitious plans to revolutionize chip packaging technology.

This move is in response to the rapidly escalating demands for computing power and memory bandwidth, driven largely by the burgeoning fields of artificial intelligence and high-performance computing.

During its recent North American Technology Symposium, TSMC announced its strategy to expand the physical scale of its chip packaging with a new generation of CoWoS (Chip-on-Wafer-on-Substrate) technology. This innovation will allow the assembly of multi-chiplet processors significantly larger than those currently available.

The current CoWoS solutions from TSMC can accommodate interposers of up to 2,831 mm², already more than three times the size of a standard photomask reticle, which is constrained to 830 – 858 mm² by the limitations of EUV lithography.

In practical terms, these technological advancements are being applied in products such as AMD’s Instinct MI300X and Nvidia’s B200 GPUs. These products already utilize large compute chipsets paired with stacks of high-bandwidth memory.

However, as AI applications continue to grow, the demand for even more silicon intensifies, prompting TSMC to develop the CoWoS-L packaging technology. Scheduled for launch as early as next year, this new technology will support interposers as large as 4,719 mm² and require substrates measuring 100×100 mm.

This upgrade will support up to 12 stacks of high-bandwidth memory, a considerable leap from current standards.

The implications of TSMC’s advancements are profound. Chips built with the new CoWoS-L technology are projected to deliver over three and a half times the compute performance of today’s leading designs.

This capacity could potentially cater to the needs of next-generation processors, such as Nvidia’s Rubin GPUs. Moreover, TSMC is not stopping there.

The company plans to push further with an even larger package, featuring a 7,885 mm² interposer on a 120×150 mm substrate. This massive assembly could accommodate four 3D-stacked systems-on-integrated chips, twelve HBM4 memory stacks, and multiple input/output dies, setting a new standard for performance and integration.

For clients with extreme performance requirements, TSMC is offering its System-on-Wafer (SoW-X) technology, which integrates entire wafers into a single chip.

While currently utilized by only a few companies like Cerebras and Tesla for specialized AI processors, TSMC anticipates broader adoption as the demand for super-sized chips rises.

However, the engineering challenges that accompany these mammoth processors are formidable. Delivering power to such large, multi-chiplet assemblies necessitates innovative solutions, given that they can draw kilowatts of power, far beyond the capabilities of traditional server designs.

To address this, TSMC is embedding advanced power management circuits directly into the chip package using its N16 FinFET technology. This includes monolithic power management ICs and on-wafer inductors integrated into the CoWoS-L substrate, allowing efficient power routing and improved power integrity.

Furthermore, embedded deep trench capacitors stabilize electrical performance by filtering out voltage fluctuations, ensuring reliable operation under heavy computational loads.

This shift towards system-level co-optimization, where power delivery, packaging, and silicon design are intertwined, marks a significant development in the semiconductor industry. Nonetheless, the transition to larger chip packages is not without its hurdles.

The increased physical size of the new substrates challenges existing module standards like OAM 2.0 and may necessitate new system and board design approaches.

Thermal management presents another critical challenge. As processors increase in size and power consumption, they generate vast amounts of heat.

Manufacturers are investigating advanced cooling techniques, including direct liquid cooling and immersion, to maintain efficient chip operation.

TSMC has already partnered with various firms to develop immersion cooling solutions for data centers, which can significantly reduce energy consumption and stabilize chip temperatures, even under intense loads.

However, the integration of these cooling technologies directly into chip packages remains a challenge for future exploration.

In summary, TSMC’s pioneering efforts to expand chip packaging technology herald a new era in the semiconductor industry. As AI and high-performance computing continue to push the boundaries of technology, TSMC’s innovations are poised to meet these challenges head-on, setting the stage for unprecedented advances in computational power and efficiency.